(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a composite intermetal dielectric, (IMD), layer, which exhibits low stress on underlying metal and dielectric structures, located on a semiconductor substrate.
(2) Description of the Prior Art
Intermetal dielectric, (IMD), layers have been used in the semiconductor industry to passivate underlying metal interconnect structures, as well as to provide isolation of these same metal interconnect structures. Low k dielectric layers, such as hydrogen silsesquioxane, (HSQ), and fluorinated silicon oxide glass, (FSG), have provided the desired passivation, and isolation characteristics, as well as offering decreased capacitances, when compared to higher k dielectric layers, such as silicon oxide. However the superior passivation characteristics of silicon oxide layers, such as minimum leakage, and high dielectric breakdown strengths, still make it an attractive candidate for IMD purposes, when compared to the lower k dielectric layer counterparts.
One problem still encountered with IMD layers, comprised with chemically vapor deposited, (CVD), silicon oxide layers, is the inherent stress of these layers, and the damage these stresses can place on underlying elements of the semiconductor device. For example an IMD layer, can be a composite IMD layer, comprised of: an underlying layer, or a IMD-1 component, such as a plasma enhanced silicon oxide layer, formed using silane as a source, an IMD-2 component, featuring a sub-atmospheric, chemically vapor deposited, (SACVD), silicon oxide layer, and an overlying, capping, plasma enhanced silicon oxide layer, (IMD-3), component, formed using tetraethylorthosilicate, (TEOS), as source. The IMD-2 component, in this case SACVD silicon oxide, which is needed to provide the desired leakage and dielectric breakdown characteristics, inherently is comprised with a high tensile stress, which induces unwanted concave or bowing up, of the underlying semiconductor substrate. This type of bowing can result in cracking of underlying insulator layers, as well as disruptions, or opens, in underlying metal interconnect patterns. The capping dielectric layer, or the IMD-3, component, formed from plasma enhanced chemical vapor deposition, using TEOS sa a source, inherently is comprised with a compressive stress, which supplies a convex, or bowing down effect, on the underlying semiconductor, and it""s elements. However the degree of compressive stress, provided by the IMD-3, PETEOS silicon oxide layer, formed using conventional deposition conditions, may not be sufficient to overcome the high tensile stress of the IMD-2, SACVD silicon oxide component, therefore still risking deleterious concave, or bowing up, effects.
This invention will teach a process for formation of PETEOS silicon oxide layers, in which the compressive stress of the layer is increased, when compared to counterpart, PETEOS silicon oxide layers, formed using conventional deposition conditions, or formed using a set of conditions, different than the deposition parameters described in this invention. The PETEOS layer, described in this invention, and used as the IMD-3 component, provides the level of compressive stress needed to balance the tensile stress of the IMD-2 component, resulting in a composite IMD layer, providing little, unwanted, tensile stress, and bowing up phenomena, of underlying elements. Prior art, such as Roy, in U.S. Pat. No. 4,631,804, Jang, in U.S. Pat. No. 5,856,230, and Purdes, in U.S. Pat. No. 4,830,984, show methods of reducing stress, and semiconductor wafer warpage, by addressing the process conditions used to form polysilicon and epitaxial silicon layers, as well as addressing the conditions used to form field oxide isolation regions. However none of these prior arts describe the novel procedure, taught in this invention, featuring a unique set of deposition conditions, used to form a PETEOS silicon oxide layer, with high compressive stress, used as a component of a composite IMD layer.
It is an object of this invention to form a composite IMD layer, to overlay, and passivate, underlying metal interconnect structures.
It is another object of this invention to form a composite IMD layer, in which the tensile stress of the composite IMD layer is reduced to a level in which a concave bend, or bowing up, of the semiconductor substrate, and the elements located on the semiconductor substrate, is eliminated.
It is another object of this invention to use a PETEOS silicon oxide layer, as a capping layer, or as a component of the composite IMD layer, where the PETEOS silicon oxide layer is formed using deposition conditions which allow the PETEOS silicon oxide layer to feature a high compressive stress, at a level needed to balance the tensile stress, inherent in an underlying component of the composite IMD layer.
In accordance with the present invention a method of forming a composite IMD layer, featuring a capping, PETEOS silicon oxide layer, comprised with a high compressive stress, and used to balance the tensile stress of underlying components of the composite IMD layer, is described. After formation of metal interconnect structures, communicating with underlying conductive regions, either on, or in a semiconductor substrate, an underlying component, (IMD-1), comprised of a thin PECVD silicon oxide layer, formed using silane as a reactant, is deposited, conformally coating the underlying metal interconnect structures. A second component of the composite IMD layer, (IMD-2), comprised of a sub-atmospheric chemically vapor deposited, (SACVD), silicon oxide layer, comprising a high tensile stress, is deposited overlying IMD-1. A third silicon oxide component, (IMD-3), of the composite IMD layer, is next formed via PECVD procedure, using TEOS as a source. The PETEOS silicon oxide component is formed using specific power and frequency deposition conditions, needed to obtain an IMD-3 silicon oxide layer, with a high compressive stress, neutralizing, or balancing the tensile stress, contained in the IMD-2 silicon oxide component, thus resulting in a composite IMD layer that does not warp or bend the semiconductor substrate due to tensile stresses.